X-CPLD-38
X-CPLD-38
Description
User defined hardware design
Often, special digital circuits are required that can be realized neither with the already available modules nor by software. This is where the X-CPLD-38 module comes into play. This module provides 38 digital inputs/outputs that are connected to a CPLD (IC4) with 288 macro-cells (Xilinx 95288XL). The bus interface to the X-Bus, including interrupts and all configuration registers, is located in a preprogrammed second CPLD (IC1). This allows the developer to concentrate on his actual task.
Timer
An additional timer (82C54) can be programed via CPLD IC1. Clock, gate and output pins of the timer are connected with CPLD IC4 and can be used.
Development software
WebPack™ (for Windows PCs), the development software for the CPLD, can be downloaded free of charge via the Internet (www.xilinx.com). Programming can be carried out in VHDL, Verilog or ABEL, simulation is possible as well.
Example
SORCUS supplies an application note for development and programming, an example program and the Jedec file for the second CPLD.
Specifications
Parameter | Value | Unit |
Number of external inputs and outputs | 38 | - |
Input voltage (other on request) (compatible with 5V TTL and 5V, 3,3V and 2,5V CMOS): | ||
log. 0 | < 0,8 | V |
log. 1 | > 2,0 | V |
Input Leakage Current, max. | 10 | µA |
Output voltage (compatible with 5V TTL and 3,3,V CMOS): | ||
log. 0, max. (IOL=8mA) | 0,4 | V |
log. 1, min. (IOH=-4mA) | 2,4 | V |
Output current: | ||
log. 0, min./typ. | 12/36 | mA |
log. 1, min./typ. | -12/-24 | mA |
Overvoltage protection of inputs | -0,5 ... +5,5 | V |
for pulses <10ns und <200mA | -2,0 ... +7,0 | V |
Watchdog-Timer, programable | 80 ... 270 | ms |
Timer: | ||
Number | 3 | |
Resolution | 16 | Bit |
Modes | ||
Operating temperature range | 0 ... +70 | °C |
optional-40 ... +85 | °C | |
Dimensions | 29x58x8 | mm |
Weight | 8,85 | g |
Power consumption (3,3 V) min./max. | 385/430 | mA |